Circuit Subdivision
This tutorial walks you through how to add subdivision lines, subdivide your circuit, and analyze the final netlist. The results of this subdivision are compared to the analysis of the complete circuit in order to demonstrate the accuracy of the results of the subdivision and the savings in memory.
For a detailed discussion of circuit subdivision and the use of subdividers,
please refer to the "Circuit Subdivision” chapter in the Sonnet User’s
Guide.
The circuit, an edge-coupled microstrip bandpass filter, is a fairly simple example of a circuit which you might decide to subdivide. In addition, it is not a very good filter design. This circuit was chosen for the purposes of clarity in explaining circuit subdivision.
You will use four vertical subdivision lines to split the circuit into five sections as shown below.
Obtaining the Example File
You use the example file, subdivide.son, for this example. You can obtain a copy of this file from the Sonnet Examples. If you do not know how to obtain a Sonnet example, select Help => Examples from any program menu, then click on the Instructions button. If you are reading this in PDF format, click on the link above.
Open
the project subdivide.son in the project editor.
The circuit appears as shown below.
Adding the Subdivision Lines
The first step in subdividing a circuit is to place the subdivision
lines that indicate where you wish to split your circuit. Subdivision
lines should be placed in locations where there is negligible coupling
across the lines. The best place to put subdivision lines in the example
used here is at points in the circuit on the coupled lines as far from
the discontinuities as possible. Therefore, a vertical subdivision line
will be placed in the middle of each coupled pair of polygons.
Each coupled pair of polygons is 595 mils in the x direction. Subdivision
lines must be placed on the grid. The closest value to halfway which still
remains on the grid is 295 mils. For the first subdivider, you must take
into account the feedline polygon which is 100 mils
in length. Therefore, the first subdivision line should be placed at 100
mils + 295 mils = 395 mils from the left box wall.
Select Tools
=> Add Subdivider from the project editor menu while holding down
the shift key.
TIP: Holding
down the shift key allows you to enter multiple subdivision lines without
having to select the command multiple times.
Since there were no subdivision lines in the circuit when you selected
the Add Subdivider command, the Subdivider Orientation dialog box appears
on your display.
All subdividers in your circuit must have either a vertical (up-down)
orientation or a horizontal (left-right) orientation on the substrate.
Click on the vertical radio button
to select the vertical orientation for your subdividers.
This sets the orientation for all subdividers subsequently added to
your circuit.
This dialog box does not appear again if you select Tools
=> Add Subdivider. The new subdivider assumes the same orientation.
If all the subdividers are deleted from a circuit, then when the Add Subdivider
command is used again, this dialog box appears.
Click
on the OK button to apply your selections and close the dialog box.
The cursor changes to indicate that you are adding subdivision lines
and a line appears which moves with your cursor.
Move
your cursor until the X coordinate of the cursor position in the status
bar is 395.0 and click.
A line representing the subdivider appears in the vertical plane running
through the point at which you clicked. The sections of the circuit are
now labeled ”s1” and ”s2”. Subdivision sections are labeled from left
to right, or top to bottom, depending upon orientation. These labels are
always sequential and are non-editable.
Subdivision lines are always snapped to the grid and may not be placed
on top of each other. Once a subdivider has been added to your circuit,
you may edit the subdivider as you would any other object in your geometry.
You may click on the subdivider and move it. You may also control the
display of the subdivider lines and labels in the Object Visibility dialog
box, invoked by selecting View ? Object Visibility from the project editor’s
main menu.
Since each of the coupled line segments are 595 mils long and you wish
to place the subdivision lines at the halfway point, each subsequent subdivision
line should be placed 595 mils further to the right in the circuit. So
the second subdivision line should be placed at 990 mils from the left
box wall.
Move the cursor until the X coordinate
is 990.0 in the status bar and click to place the second subdivision line.
The subdivision line appears on your circuit and the sections are relabeled
as shown below.
Add
subdividers at 1585 mils and 2180 mils from the left box wall.
Once you have completed adding all the subdivision lines, press the
Escape key to return to pointer mode. Your circuit should now appear like
this:
Setting Up Circuit Properties
For this example, the circuit properties such as box size, dielectric
layers, metal materials, etc. have already been input in the example circuit.
It is important to have the circuit properties input before performing
the subdivide since these are the properties used for all the subprojects
created as the result of the subdivide. If you do not enter all the desired
properties, you will need to enter them individually in each subproject
or modify the original source project and execute the subdivide again.
For this example, you will analyze the netlist using an adaptive
sweep (ABS) with Hierarchy Sweep turned on. When the Hierarchy Sweep
option is used, the analysis control settings for the netlist are used
to analyze all the subprojects in the netlist. The desired frequency band
for the circuit is 2.3 GHz to 2.5 GHz. An adaptive sweep provides approximately
300 data points.
Select
Analysis => Setup
from the main menu.
The Analysis Setup dialog box appears on your display.
Select
"Adaptive Sweep (ABS)" from the Analysis Control drop list if
it is not already selected.
This selects the Adaptive Sweep as your type of analysis. The adaptive
sweep provides a fine resolution of response data over the given frequency
band. Note that the text entry boxes are updated to reflect your choice
of analysis.
Enter
2.3 in the Start box and 2.5 in the Stop box.
This sets up the analysis frequency band. This analysis setup is duplicated
in all of the geometry subprojects when the subdivide is executed, as
well as in the main netlist. The Analysis Setup dialog box should appears
as shown below.
Click on the OK button to save the analysis setup and close the dialog box.
Select
File => Save from the
main menu.
The file must be saved before executing the subdivide. The position
of the subdivision lines are saved as part of your source project.
Subdividing Your Circuit
The actual subdivision of the project is executed by the software but
you must enter names for the resulting main netlist file and subproject
files produced as well as, optionally, defining a feedline
length to be added to the subprojects.
Feedlines should be added to the subprojects if
you feel it necessary to move discontinuities in the various sections
of the circuit further away from the boxwalls to prevent
any interaction between the discontinuities and boxwalls.
This can provide a more accurate analysis result for each section of the
circuit. Any added feedlines are of lossless
metal, regardless of the metal type to which they are attached.
Sonnet software provides a default recommended value for the feedline
or you may enter your own value.
Select
Tools => Subdivide
Circuit from the project editor main menu.
The Circuit Subdivision dialog box appears on your display.
The
name "subdivide_net.son" is provided by default in the Main
Netlist Project text entry box.
This name is used for the main netlist which connects the geometry
projects resulting from the subdivide. The default name is the basename
of the source project with a "net" added on. You may use any
project name you wish but it must be different than the project name of
the source file.
If you wish to change the directory in which the resulting files are
created, click on the Browse button to open a browse window. If you select
an existing project file, you are prompted if you wish to overwrite the
existing file.
Click
on OK to set the name and close the dialog box.
The Subproject Specifications dialog box appears on your display as
shown below. This dialog box allows you to enter names for each of the
geometry subprojects that result from performing the subdivide. Default
names, consisting of the main netlist project name with the section number
added, are provided but may be edited. For this example, use the default
names.
The names for the subprojects must be unique and must be different
from the source project name and main netlist name.
The suggested length option is already selected for the feedline
length. This feedline of lossless metal is added to
ports generated when the subdivide is executed.
To enter your own feedline length, you would select
the fixed length radio button and enter the value in the corresponding
text entry box. Select the None radio button if you do not wish to add
a feedline.
Click
on the Subdivide button to execute the subdivide.
The main netlist and subprojects are created using the names input
by you. The main netlist project is opened in the project editor.
The main network is defined as subdivide_net and
has two ports. This corresponds to the source circuit. There is a project
(PRJ) entry line for each of the subprojects. The project
line includes the setting for the source of the analysis frequencies.
A Hierarchy sweep, in which the netlist frequency sweep is imposed on
all the project elements, is on by default. If you turn this off, the
project default setting of using its own sweep is displayed.
Pictured below are the geometries for the first two sections, subdivide_net_s1.son
and subdivide_net_s2.son. Note that in subdivide_net_s1.son, feedlines
with a reference plane have only been added to ports 2 and 3, the ports
created in the subdivide, but not port 1 which is contained in the source
project. All the ports in subdivide_net_s2 have feedlines
since all were created in the subdivide. Note that the feedlines
are all of lossless metal.
Analysis of the Network File
The last step to complete the analysis of the filter is to analyze
the netlist project created by the subdivide. The analysis controls you
entered in the original project are the ones you wish to use to analyze
the netlist, so the analysis setup is already complete. An adaptive sweep
from 2.3 GHz to 2.5 GHz will be performed on the netlist.
Click
on the project editor window containing the netlist to make this the active
file.
This is indicated by the title bar on the netlist being highlighted.
TIP: You
can switch the active file in the project editor by clicking on the title
bar of the project window or by selecting the project from the Windows
menu on the main menu.
Click
on the Analyze button to launch the netlist analysis.
The analysis monitor appears on your display.
The project legend indicates that subdivide_net_s1.son is being analyzed.
Em will perform an adaptive sweep on each of the five subprojects and
then use the resulting data to analyze the network. Status messages are
output under the progress bar.
There are two results that are significant to observe. A comparison
of the netlist analysis data with the analysis data from the source circuit,
and a comparison of the amount of time and memory each analysis used.
We have provided the source project file including analysis data under
the example sub_whole.son available in the Sonnet Examples.
The graph below shows the results of the netlist analysis versus the
results of a full analysis of the source project.
As you can see there is very good agreement between the two analysis
results. Both files were analyzed on the same computer. The time required
for the netlist was actually longer than the time required to analyze
the circuit as a whole because this was a simple example chosen for clarity,
and the benefits of circuit subdivision are only seen for larger circuits.
Using circuit subdivision reduces your memory requirements for analysis
of a large circuit. Each of the subprojects requires less subsections
to analyze than the complete circuit. This improvement comes as a result
of reducing the number of subsections for any given analysis since both
computation time and memory requirements rise sharply as the subsections
go up, as shown on the chart below. For this example, the entire filter
circuit used 2006 subsections while the largest individual piece only
required 1400 subsections and the smallest only required 854 subsections.
On many larger circuits the use of the automatic circuit subdivision
features in Sonnet can greatly improve the efficiency of your em
usage.
Additional Improvements
There are two other ways this circuit could have been made even more efficient. You could have refrained from adding the automatic feedlines and you could have taken advantage of the fact that some of the subprojects were virtually identical.
For the purpose of illustration, this tutorial added feedlines to all ports generated in the subdivide using the recommended length. Feedlines are added to a circuit to move the discontinuities in the subprojects far enough from the boxwalls to prevent interaction. In the case of this example, either discontinuities were not present or they were already far enough from the box wall that additional feedlines were unnecessary.
If you leave the feedlines out by selecting None in the Subprojects Specifications dialog box, the netlist analysis runs 1.5X faster than previously.
The last method that would allow you to decrease the processing time would be to use fewer subprojects in the netlist to create the circuit. Observation of the circuit geometry and response data shows that subdivide_net_s1.son and subdivide_net_s5.son are virtually identical. The same is true for subdivide_net_s2.son and subdivide_net_s4.son. You could edit the main netlist, subdivide_net.son so that you only use three files: subdivide_s1.son, subidivide_net_s2.son and subdivide_net_s3.son to create the whole circuit. This eliminates the need to calculate data for two out of five subprojects. This analysis is 2X faster than the analysis using feedlines and all five subprojects
