PI Model Spice - A High Speed Digital Example
The figure below shows the top level of a byte-reversal network. The byte order on input (left side) is reversed on output (right side). This is a top view. The arrow heads indicate connections between levels (down vias). There are 32 input ports and 32 output ports for a total of 64 ports. The first eight bits (ports 1-8) go into the circuit, down to the second level, underneath all the other lines, and come up on the right hand side as the last eight bits.
The bottom level of the byte-reversal network is shown below. The triangles indicate connections between levels (up vias).
You can get a copy of the example shown above, Br32, from the Sonnet examples. For directions on obtaining a Sonnet example, select Help => Examples from the menu of any Sonnet program, then click on the Instructions button.
The analysis control for circuit is set to analyze at 10 and 15 MHz, where each line is about 1 degree long. To create a lumped model, perform the following:
1. Open br32.son in the project editor.
2. Select Analysis => Output Files from the project editor main menu.
The Generate Default Output Files dialog box appears.
3. Click on the PI Model button in the Generate Default Output Files dialog box.
The PI Model File Entry dialog box appears.
4. The defaults of a PSpice file by the name of br32.lib appear. Since this is the correct setup, you do not need to change any settings in this dialog box.
5. Click on the OK button to close the PI Model File Entry dialog box.
The name ”br32.lib” appears in the Output File List in the Generate Default Output Files dialog box.
6. Click on the OK button in the Generate Default Output Files dialog box.
7. Save br32.son.
8. Select Project => Analyze from the project editor main menu to analyze the circuit.
The lumped model is stored in the file ”br32.lib”.
The following is a portion of the resulting SPICE model ( ... indicates information left out):
.subckt SonData 1 2 3 4 . . . 63 64 GND
C_C1 1 GND 14.4632pf
C_C2 1 2 1.06465pf
C_C3 1 9 0.044715pf
C_C4 1 10 0.037854pf
.
C_C1426 64 GND 9.099054pf
L_L1 1 33 77.25012nh
L_L2 2 34 77.30183nh
L_L3 3 35 77.35662nh
.
.
.
L_L32 32 64 79.6777nh
Kn_K1 L_L1 L_L2 0.166483
Kn_K2 L_L1 L_L3 0.050502
.
.
.
Kn_K176 L_L31 L_L32 0.177254
Nodes 1 - 64 correspond to the ports of the same number in the circuit layout, . Node 0 is ground. For example, C1 represents the capacitance from port 1 to ground. L1 represents the inductance from port 1 to port 33 (i.e., port 1 is connected to port 33). There is also a capacitance (not listed above) from port 33 to ground.
C2 is a stray capacitance coupling ports 1 and 2, generating cross-talk. The capacitive coupling causes cross-talk whenever there is a time varying voltage difference between ports 1 and 2.
Mutual inductance K1 inductively couples the port 1 to port 33 line (L1) to the port 2 to port 34 line (L2), also generating cross-talk. The mutual inductance causes cross-talk whenever either the port 1 or port 2 line carries a time varying current. A quick inspection of this file reveals the worst cases for cross-talk (i.e., largest mutual inductors and capacitors).
A SPICE analysis was performed using the em synthesized model of the byte-reversal network. Shown below is the cross-talk to the port 25 - port 57 line caused by a 1 Volt signal with a 10 pS rise time on port 1. All ports are terminated in 50 ohms. Analysis courtesy of CONTEC Microelectronics USA.
